1. Field of the Invention
The present invention relates to semiconductor devices, more particularly to a fine-geometry semiconductor device having a capacitor of high reliability.
2. Description of the Background Art
Referring to FIG. 36, an underlying interlayer insulation film 103 such as of a silicon oxide film is layered on a silicon substrate 101. An insulation film 105 such as of a silicon nitride film and/or a metal oxide film is disposed on underlying interlayer insulation film 103. An interlayer insulation film 107 such as of a silicon oxide film is deposited on insulation film 105. Insulation film 105 included in interlayer insulation film 107 can be conceived as a portion of interlayer insulation film 107.
This semiconductor device is mainly divided into a capacitor region where capacitors are provided and a mark and TEG (Test Element Group) region. The mark and TEG region including the peripheral circuit region in a DRAM (Dynamic Random Access Memory) is referred to as a peripheral region. A storage node 111 forming the lower electrode of the capacitor is provided within interlayer insulation film 107 in the capacitor region. In accordance with the microminiaturization of semiconductor devices, the thickness of the doped polycrystalline silicon forming the storage node has been reduced to achieve a larger capacitance of the capacitor. Reducing the thickness of this doped polycrystalline silicon film has induced the problem that a contact of the storage node is not feasible in the TEG region (refer to Japanese Patent Laying-Open No. 2001-339050, for example).
In addition to the above-described formation of a storage node using doped polycrystalline silicon, storage node 111 is formed of noble metal such as ruthenium (Ru) and platinum (Pt), or refractory metal such as tungsten (W). A plug interconnection 109 establishing electrical connection between storage node 111 and the silicon substrate is provided so as to pierce underlying interlayer insulation film 103. In the peripheral region of the layer identical to that of storage node 111, an alignment mark 113 required in photolithography, i.e., an overlay inspection mark or exposure system alignment mark, is formed. Alignment mark 113 is formed at the same step as storage node 111. Therefore, storage node 111 and alignment mark 113 are formed of the same material.
In the case where noble metal such as ruthenium or platinum is employed for storage node 111, the low adherence between storage node 111 and underlying insulation film 103 becomes problematic. In the subsequent annealing or oxidation process, particularly in the case where Ta2O5 is employed for the capacitor dielectric film, the storage node will easily peel off during the oxidation process (or crystalline process) of Ta2O by the ozone (O3). Delamination of alignment mark 113 at the region extending on the surface of interlayer insulation film 107 in the peripheral region, such as portion “A” in FIG. 36 is particularly noticeable.
FIG. 37 shows a modification of the conventional semiconductor device of FIG. 36. Referring to FIG. 37, storage node 111 is of a cylindrical configuration with the tubular metal film protruding upwards. This cylindrical storage node is obtained by forming a hole in interlayer insulation film 107 of FIG. 36 and subjecting this hole to vapor deposition of a noble metal film such as Ru or Pt. The noble metal film is vapor-deposited to a predetermined thickness and then subjected to polishing by chemical mechanical polishing (CMP) or etching to have the portion other than that corresponding to the storage node removed. Then, interlayer insulation film 107 is removed by using a wetting solution such as HF. FIG. 37 is a sectional view of the semiconductor device after interlayer insulation film 107 has been removed.
In FIG. 37, storage node 111 and alignment mark 113 both have a cylindrical configuration. In the peripheral region, it is difficult to keep respective alignment marks in position as compared to the capacitor region. Configuration control could not be achieved. As a result, a cylindrical alignment mark formed at the same step as the storage node has the disadvantage of readily inducing mechanical fracture. A metal film with mechanical fracture will cause a short circuit in the semiconductor device by dispersion and reattachment during the processing steps. Thus, the reliability of the semiconductor device will be degraded.